1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device in which stored data can be electrically rewritten.
2. Description of the Prior Art
Of electrically rewritable nonvolatile memory devices (to be referred to as EEPROMs hereinafter), a nonvolatile semiconductor memory device including storage elements constituting a large number of memory cells and having a function of simultaneously erasing these memory cells is called a flash memory. This memory device is one of storage elements currently most often used as large-capacity nonvolatile semiconductor memory devices and its market is expected to grow further in the future.
Several structures have been proposed as the structure of nonvolatile semiconductor storage elements for memory cells of this flash memory. As one representative example, a sectional view of the structure of a stack gate type storage element is shown in FIG. 1.
In this storage element, an insulating film 3 (usually an Si oxide film and called a first gate oxide film in this example) having a thickness of about 10 nm is formed on a p-type Si substrate 1. Additionally, a floating gate 5 (usually polysilicon) having a thickness of about 50 nm, an insulating film 7 (usually an Si oxide film and called a second gate oxide film in this example) having a thickness of about 20 nm, and a metal control gate 9 are stacked in this order on the first gate oxide film 3. N-type diffusion layers serving as a source 11 and a drain 15 are formed on the two sides of the gate on the substrate 1.
This general nonvolatile semiconductor storage element is used as a storage element 17 constituting one memory cell. A nonvolatile semiconductor memory device is formed by arranging a large number of these storage elements 17 in the form of arrays on the Si substrate 1.
A data write in this storage element 17 will be described below.
To write data "0" in the storage element 17, voltages of +6 V and +10 V, for example, are applied to the terminal of the drain 15 and the control gate 9, respectively, and the source 11 and the Si substrate 1 are grounded (0 V). At this time, the potential of the floating gate 5 is unconditionally determined by the capacitances of the first and second gate oxide films 3 and 7.
Under the conditions set as above, a channel formed in the surface of the Si substrate 1 immediately below the floating gate 5 is pinched off by a depletion layer 15a formed near the drain. In this depletion layer 15a, electrons and holes (to be referred to as hot electrons and hot holes, respectively, hereinafter) having high kinetic energy are generated by impact ionization.
These hot carriers have energy by which they can tunnel an energy barrier in the first gate oxide film 3. Of these hot carriers, hot electrons are accelerated by an electric field between the floating gate 5 and the depletion layer 15a and injected into the floating gate 5.
This injection of the hot electrons gradually lowers the potential of the floating gate 5. When the electric field between the floating gate 5 and the depletion layer 15a becomes zero, the hot electron injection is complete. As a result of this operation, the threshold voltage (to be referred to as the Vth hereinafter) of the transistor of a storage element A rises from about 0.5 V before the write to about 5 V. This state is defined as a state in which data "0" is written.
As described above, the operation of injecting hot electrons into the floating gate 5 of the storage element 17 constituting a memory cell and raising the Vth is called a write. When the applied voltage to the control gate 9 is returned to 0 V, the electrons stored in the control gate 9 remain in the control gate 9, and this state is held for very long periods of time. Accordingly, this element serves as a nonvolatile semiconductor storage element capable of holding stored information for long time periods even after the electrical signal is cut off.
An erase of data "0" will be described next.
To erase data "0", the control gate 9 and the Si substrate 1 of the storage element 17 are grounded (0 V), and the drain 15 is opened. A voltage of 9 V is applied to the source 11.
Under the above voltage set conditions, the potential of the floating gate 5 is unconditionally determined by the voltage set conditions.
The breakdown voltage of the p-n junction of the source 11 with respect to the Si substrate 1 is preset to about 7 V. Therefore, when the 9-V voltage is applied to the source 11, hot carriers are generated by breakdown in a depletion layer 11a near the source. Of these hot carriers, hot holes are injected into the floating gate 5 by an electric field between the floating gate 5 and the depletion layer 11a near the source.
This injection of the hot holes raises the potential of the floating gate 5. The injection is complete when the electric field between the depletion layer 11a and the floating gate 5 becomes zero. Consequently, the Vth of the memory cell drops and returns to about 0.5 V.
As described above, the operation by which hot holes are injected into the floating gate 5 of the storage element 17 of a memory cell and as a consequence the Vth drops and returns to the original voltage is called a data erase. Also, the method of erasing data by injection of hot holes as described above is particularly called hot hole injection.
Another data erase method using a current (to be referred to as an FN current hereinafter) produced by a Fowler-Noldheim tunnel will be described below.
In the data erase using an FN current, +12 V are applied to the source 11, the Si substrate 1 and the control gate 9 are grounded (0 V), and the drain 15 is opened or grounded (0 V). To erase data using an FN current, the breakdown voltage of the p-n junction between the source 11 and the Si substrate 1 is preset to 12 V or more.
In writing data "0", therefore, the potential of the floating gate 5 is negative, so a potential difference is further produced accordingly. Consequently, a strong electric field of 10 MV/cm or more is applied to the first gate oxide film 3 between the source 11 and the floating gate 5. When such a strong electric field exists, an FN current flows in the gate oxide film due to a tunnel effect. By extracting electrons stored in the floating gate 5 toward the source 11 by using this FN current, data can be erased.
Since the breakdown voltage of the p-n junction is high, 12 V or more, the generation of hot carriers need not be taken into consideration.
Of the data erase methods described above, however, even in the method using hot hole injection or an FN current, the Vth of the storage element 17 of a memory cell when data is erased and written varies to a certain degree.
FIG. 2 shows conventionally found common Vth distributions when data write and erase are performed for a plurality of storage elements 17.
In this prior art, the center of the Vth's of the storage elements 17 after erase is approximately 0.5 V as indicated by D1, and these Vth's have a distribution of about 1 V on each of high and low sides (refer to range a.sub.1). Analogously, the Vth's after write center around 6 V as indicated by D2 and have a distribution of about 1 V on each side (refer to range a.sub.2).
Of these Vth distributions, the variation after data erase is particularly a problem. For example, in a storage element D3, in which the Vth is 0 V (ground potential) or less (a memory cell formed by a storage element like this is called an overerased cell), of a number of storage elements shown in FIG. 2, the transistor is normally ON, so the drain current constantly flows.
Accordingly, all memory cells in a memory cell block having a common digit line with this overerased cell cannot perform reads and writes. Consequently, this nonvolatile semiconductor memory device ceases to function normally.
An overerased cell exists for the reason explained below. As shown in FIG. 2, in the data erase using hot hole injection, the Vth after data in a memory cell is erased is affected by the amount of hot holes injected into the floating gate 5 within a predetermined period during the data erase. This hot hole injection amount is determined by the electric field between the floating gate 5 and the depletion layer 15a near the drain during the data erase. Therefore, if the electric field between the floating gate 5 and the depletion layer 11a near the source differs from one memory cell to another, the Vth during data erase also varies from one memory cell to another.
The potential of the floating gate is determined by the thicknesses and dielectric constants of the first and second gate oxide films 3 and 7, and by the potentials of the control gate 9, the source 11, and the Si substrate 1. Therefore, if the thickness of the gate oxide film or the overlap between the gate and the source differs from one storage element 17 to another, the potential of the floating gate 5 also varies. This produces a difference in the electric field between the floating gate 5 and the depletion layer 15a near the source. Consequently, the charge extraction amount varies to produce a variation in the Vth's of the storage elements 17 of individual memory cells.
On the other hand, in the data write using an FN current, electric charge extracted from the floating gate 5 to the source 11 is similarly influenced by the electric field between the floating gate 5 and the depletion layer 11a near the source. This results in a variation in the Vth's of storage elements of memory cells.
As a first method of solving the above problem, efforts are being made to uniformize the physical structures of the storage elements 17 constituting individual memory cells, i.e., minimize the thicknesses of the first and second gate oxide films 3 and 7 and the overlap between the source and the gate by improving the process techniques and the like. However, as the transistors constituting memory cells shrink further, the thicknesses of gate oxide films continue to decrease while the capacities of memories continue to increase. Consequently, some measure other than the above measure is being required.
To solve the above problems, several measures have been proposed.
As an example, Japanese Unexamined Patent Publication No. 5-258583 has disclosed a method by which an overerased cell is eliminated by applying a voltage of 14 V (a voltage higher than 12 V as a normal erase voltage is chosen) to the sources of a plurality of memory cells from which data is to be erased (in the disclosed method, -14 V are applied to the control gates), and then applying a high voltage of -14 V to the sources (in the disclosed method, +14 V are applied to the control gates).
In this method, even if storage elements after erase have a variation in the Vth's (even if an overerased cell exists), the electric field between the floating gate 5 and the depletion layer 11a near the source is increased in this overerased cell when a high voltage of -14 V is later applied. Since this increases the electric charge amount extracted from the floating gate 5, the Vth's of the storage elements 17 constituting memory cells can be finally made uniform.
Unfortunately, when the above method is used it is necessary to continuously apply positive and negative high-voltage pulses twice in a data erase. This not only complicates the data erase but also prolongs the erase time. Additionally, since the positive and negative high-voltage pulses must be continuously applied, the gate insulating film or the like readily fatigues. Therefore, it has been pointed out that the reliability of a memory operation impairs or the life as a storage element shortens.
Furthermore, the above complicated operation must be equally performed for all memory cells because not so many overerased cells exist among a very large number of memory cells.